TSMC’s insecure silicon roadmap may also mean significant issues for your Apple devices

Taiwan Semiconductor Manufacturing Company (TSMC) actually held its 2024 North America Technology Symposium, where it informed attendees and partners about its technology roadmap for the future.

You might reasonably ask: okay but what does this have to do with me, a user of Apple products? Well, TSMC is a chip fabrication company, and arguably the most advanced one in the industry. They’ve been Apple’s partner for the vast majority of its key chips—the A series for iPhones and iPads, the M series for Macs, and more. And Apple is typically first in line for new manufacturing processes from TSMC, paying a premium to be the first customer to use 5nm or 3nm technologies, for example.

Here’s a summary of the TSMC roadmap and what it could mean for future Apple silicon, and therefore future iPhones, iPads, Macs, and more.

What’s a nanometer?

Before we discuss TSMC’s future technologies, let’s take a short reminder on what a “nanometer” is in this context. Technically, it’s one billionth of a meter. A human hair is between 50,000 and 100,000nm thick. Most bacteria are between 1,000 and 10,000 nanometers.

In silicon process technology, the “nanometer” measurement refers to how small certain aspects of the chip are. Different companies measure different aspects—it used to be the scale between the source and drain parts of a field-effect transistor (FET), but today various parts are measured by different companies.

In other words, 5nm means some specific parts of the chip are only 5 nanometers in size, but TSMC’s 5nm process is not the same as Intel’s 5nm, nor the same as Samsung’s 5nm, and many others. A smaller nanometer number means you can fit more chip logic, cache, or other components in the same amount of space, which can lead to more powerful chips, lower power consumption, smaller chips that fit into smaller devices, and other benefits.

Think of it like viewing a city in Apple Maps—zooming out makes everything smaller, allowing more buildings, streets, and land to fit on the same screen. That’s what moving to a smaller nanometer process is like: fitting more ‘city’ into the same space.

There are many other important aspects of a microprocessor, including how transistors are insulated, the materials used, and much more, but the ‘nanometer’ measurement has become a standard way of distinguishing one major manufacturing generation from another.

3nm progress

Apple was first to use TSMC’s initial 3nm process, which was called N3. The company has since refined it with the N3E process, which is what we expect Apple will use in its most advanced products this fall (A18 and M4). While this may seem significant, the primary goal of N3E is to make the chips more cost-effective. There are minor differences in density and performance, but it is not a major generational shift.

2nm coming subsequent Twelve months

The next major change is the shift to 2nm, which is expected to occur in 2025. Apple is once again expected to be the first major (and possibly only) customer, so it’s likely that the A19 or other chips (perhaps an M5?) shipping in late 2025 will use this process. It all comes down to TSMC’s ability to resolve manufacturing kinks and yields in time to produce tens of millions of chips with it.

Compared to the N3E process, the N2 process is expected to reduce power consumption by 25–30 percent (for a chip of the same complexity and frequency) or to increase performance by 10–15 percent at the same power consumption. Chip density (how much fits into a single area) is expected to increase by 15 percent.

A notable change in this generation of chips, beyond simply being smaller, denser, and faster, is something TSMC calls “NanoFlex.” This will allow chip designers to use cells from different chip libraries on the same wafer. Typically, a chip designer must use all blocks from a “low power,” “high density,” or “high performance” library, depending on the chip’s primary needs. By enabling designs to use different parts from different libraries, chips can fine-tune various areas to their specific requirements.

For example, Apple may decide that it is most important to make the video and audio encoders and decoders portion of the chip as small as possible and implement that portion using the high-density design libraries, while using the energy-efficient libraries for the low-power CPU cores and the high-performance libraries for the performance CPU cores.

For the chips Apple produces, the limiting factor tends to be energy and thermal dissipation. So that potentialities are you’ll well be ready to presumably query chips made with the N2 process to web extra “stuff” in them (cores, cache, bigger and additional complex video encoders, etc) to the tune of 15-20 p.c, with a dinky bit elevated clock speeds and therefore performance, when when compared with chips from the Twelve months earlier than. Nonetheless, the flexibility to optimize particular parts of the chip with instruments from diverse chip libraries has the capability to pay off enormous with regards to elevated “top” performance or decrease lazy energy.

The year after N2 is released, TSMC will introduce two enhanced versions of the process: N2P, which focuses on high performance, and N2X, which focuses on lower voltages and power consumption. It is unclear whether Apple will adopt either of these for the chips that come out in 2026.

A16—are we using angstroms now?

The most critical shift after 2nm (N2) is a process TSMC calls A16 (no relation to the A16 Bionic). It’s a 1.6-nanometer process but now that issues are getting so tiny, they’re producing of getting off “nanometers” and switching to “angstroms.” An angstrom is a ten-billionth of a meter, or 10 times smaller than a nanometer.

This one is now not coming till gradual 2026, nearly indubitably too gradual for Apple to make declare of that Twelve months. We’ll compare chips made with the A16 process from Apple in 2027, presumably.

TSMC gave some early estimates when compared to the upcoming N2P process, where A16 is predicted to boost performance by 8-10 percent at the same voltage and complexity or reduce power by 15-20 percent at the same frequency and transistor count.

The major innovation in the A16 generation may be backside power delivery, something TSMC calls “Super Power Rail.” This runs a network for power distribution on the back side of the silicon wafer, connected to the transistors through tiny tunnels through it. This improves density and possibly reliability, as power doesn’t need to be routed around with all of the signal and clock distribution lines on the top side of the chip. Other chip manufacturers are pursuing similar technologies (Intel’s PowerVia comes to mind)—typically different approaches to the same idea.

TSMC may also be a bit later than competitors like Intel with this kind of technology, because it has been pushed back a bit. It was initially expected to debut in the N2P process, and now may be first launched in A16 as an alternative.

Chips in Apple products that use the A16 process may be able to fit even more components (more cores, larger caches) than the N2 process while maintaining the same power profile.

Having chips with higher density or a better power profile earlier than others is certainly one of Apple’s major advantages, but the real magic comes from excellent chip design and software engineering that optimizes Apple’s software specifically for the chips they produce.

Author: Jason CrossSenior Editor